There are numerous devices comprising silicon layers containing deep or high aspect ratio trenches. Forming such deep trenches in the silicon layer of these devices provides many novel and promising structures. The types of devices containing such trenches include the numerous types of silicon-based MEMS devices, as well ICs.
In IC fabrication, devices such as transistors may be formed on a semiconductor wafer or substrate, which is typically made of silicon. MOSFET devices are widely used in numerous applications, including automotive electronics, disk drives and power supplies. Generally, these devices function as switches, and they are used to connect a power supply to a load. It is important that the resistance of the device be as low as possible when the switch is closed. Otherwise, power is wasted and excessive heat may be generated.
One type of MOSFET is described in U.S. Pat. No. 6,084,268, the disclosure of which is incorporated herein by reference. In another type of MOSFET, the gate is formed in a trench. See, for example, U.S. Pat. Nos. 6,084,264, 5,998,833, 5,998,836, 5,998,837, 6,049,108, 6,051,488, 5,895,952, 6,204,533, and 6,090,716, the disclosures of which are incorporated herein by reference. An example of such a device is illustrated in FIGS. 1 and 2, with FIG. 1 depicting a cross-sectional view of a single cell of a MOSFET 100, and FIG. 2 depicting a plan view of the cell. Gates 102 and 104 are formed in trenches and surrounded by gate oxide layers 106 and 108, respectively. The trench gate is often formed in a grid pattern including an array of polygonal shapes (one section of which is shown in FIG. 2), the grid representing a single interconnected gate (gates 102 and 104 being the same). The trench gate may also be formed as a series of distinct parallel stripes.
MOSFET 100 is formed in an N-epitaxial layer 110. A N+ source region 112 is formed at the surface of epitaxial layer 110. A P+ contact region 114 is also formed at the surface of epitaxial layer 110. A P-body region 116 is located below N+ source region 112 and P+ contact region 114. A metal source contact 118 contacts the source region 112 and shorts the source region 112 to the P+ contact region 114 and P body region 116.
The N-epitaxial layer 110 is formed on a substrate 120, and a drain contact (not shown) is located at the bottom of the substrate 120. The contact for the gates 102 and 104 is likewise not shown, but it is generally made by extending the conductive gate material outside of the trench and forming a metal contact at a location remote from the individual cells. The gate is typically made of phosphorus or boron doped polysilicon.
A region 111 of N-epitaxial layer 110 between the substrate 120 and the P body 116 is generally more lightly doped with N-type impurities than substrate 120. This increases the ability of MOSFET 100 to withstand high voltages. Region 111 is sometimes referred to as a “lightly doped” or “drift” region (“drift” referring to the movement of carriers in an electric field). Drift region 111 and substrate 120 constitute the drain of MOSFET 100.
One feature making the trench configuration attractive is that the current flows vertically through the channel of the MOSFET. This permits a higher packing density than MOSFETs such as described in U.S. Pat. No. 6,084,268, where the current flows horizontally through the channel and then vertically through the drain. Greater cell density generally means more MOSFETs can be manufactured per unit area of the substrate and, therefore, a lower on-resistance (RDS(on)) for the device. Increasing the cell density also allows the individual transistors to be closer together, requiring less area on a substrate or wafer and reducing the cost of manufacturing the device.
One problem standing in the way of increasing the cell density by manufacturing the transistors closer together is the alignment tolerance. The alignment tolerance is the amount of over-sizing needed to compensate for variations in the alignment. For example, as illustrated in FIG. 3, after the gate conductor 10 is placed in the trench 11, an isolation dielectric 4 is placed over the conductor 10 to electrically isolate the gate conductor from other conductive layers that will be placed on the substrate 12 during subsequent processing. Because the isolation dielectric 4 is only over the gate—and other selected—portions of the device, a masking and etching step using patterned photoresist mask 22 is employed to define the portions of the device where the isolation dielectric 4 need not be present, such as upper surface 13 of substrate 12. To compensate for the variations in the alignment of the trenches, an excess amount of the etched isolation dielectric 4A remains for adequate isolation, as depicted in FIG. 4. Because of this alignment tolerance 6, the transistors cannot be placed closer together and the cell density cannot be increased to yield the advantages mentioned above.